Project Work
By working on below projects, student will get familiar with:
- Majority of standard protocols(AXI, AHB, APB, SPI, I2C, UART, etc.)
- Industry standard simulation tools like Cadence Xcelium & Synopsys VCS
- Gain RTL debug & verification expertise
- RTL coding using Verilog, System Verilog HDL’s and test bench development using UVM
Project 1: Memory Verification using test bench with configurable number of agents.
Project 2: RTL coding of Synchronous and Asynchronous FIFO verification using UVM
Project 3: Design and Verification of SPI controller
Project 4: Ethernet MAC functional verification using System Verilog UVM
Project 5: Verification IP development for AXI3.0 protocol using System Verilog
Project 6: Many mini projects including simulation with the EDA tools during the lecture
test