This a 6 months course structured to enable students gain in depth exposure to all the aspects of VLSI design and functional verification. This is one of the exhaustive and featured courses where the course materials are prepared and delivered by 35+ years experienced US/Japan based Professionals, who designed the courses/lessons for the current demand of the Semiconductor Industry.
VLSI Design and Verification course ensures that a fresher is prepared on all the essential aspects of VLSI front end domain including ASIC flow, advanced digital design, CMOS, SOC design and verification concepts, Verilog, System Verilog, UVM, Linux, version control and scripting. Course also includes training on soft skill for effective interview performance.
Eligibility & Course Prerequisites
B.E or Mater’s Degree in Electricals or Electronics Engineering
Knowledge of C or C++ would be added advantage.
Duration of the Course/Training & Timings
6 Months including theory, practical/lab, exams and final project work.
- 26 weeks or 6 Months on Saturday and Sunday from 9AM to 1PM with 30 mins break.
- 3 Hours of live lecture session on Saturday and Sunday
- 1 Hours of live online lab session with EDA tools as and when it is applicable.
- 24×7 access to EDA tools and help on weekdays too.
Course Description
Mainly focused on enhancing the Design Verification skills needed by industry. The curriculum is designed to include the latest methodologies being adopted by industry. By end of the course you will have hands on experience in design and verification with Verilog, system Verilog (SV) in UVM methodology.
Lack of fundamentals in advanced digital design, Analog design and Verilog for design & verification becomes a major deterrent for freshers in finding right career opportunities. VLSI design and verification course offered in both classroom and online mode ensures that fresher is empowered with all the essential skill set required for various job roles in VLSI front end domain. VLSI design and verification course is practical oriented with each aspect of course involving multiple hands on projects. Student progress is tracked using 75 detailed assignments covering all the aspects from digital design, VLSI flow, SOC design & verification, basics of RTL coding, Verilog, System Verilog, RTL debug, UNIX, and PERL/Python/TCL scripting.
VLSI Design and Verification course is also targeted for engineers working in non-VLSI domains and planning to make career in VLSI.
Students planning to pursue complex projects after this course can do by paying a nominal fee. Silicon Synergy offers more than 30+ other projects based on industry standard protocols like USB3.0, PCIe, UFS, SATA, DDR, DMA, AMBA, Bridge and Ethernet MAC etc.
What Will I Learn From This Course?
- Understanding on ASIC/FPGA Design
- Deep understanding of Advanced Digital Logic concepts and Designs Verification
- Strong hands on System Verilog and UVM for Design
- Developing the Verification Plan, Functional Coverage closure, SVAs
- Regression flow
- 24×7 Lab Support with Lab practice handouts and course material
- Industry standard project execution, Lab practice and theory sessions under the guidance of industry expert with 12+ years of experience.
- Soft skills development, complete suite of job oriented ASIC Verification training with 100% placement assistance.
- Verilog, RTL Design, RTL Verification Training Institute.
Final Projects Description
Will be announced once you enroll into the course
EDA Tools & Technology Used for this Course
- EDA Tools: Synopsys VCS & Fusion Compiler Suite & Cadence Xcelium & VLSI Design Suite.
- Technology Used: 14nm FINFET & 28nm Planar MOSFET.
- Lab Access: Flexible learning with 24×7 online access to all the EDA tools that are running on high speed cloud servers in USA.
- Access EDA tools, designs and libraries anytime and anywhere in the globe through VPN.
Recommended Additional Courses
Advanced Digital Design Course: Mainly focus on all the digital design concepts including combinational logic, sequential logic, circuit design concepts, memory types and other essential things focused in majority of fresher interviews. Course assume minimal exposure to digital design concepts, it starts from basic concepts till advanced concepts including clock domain crossing, synchronizers, timing violation fixing, etc.
Verilog/RTL Coding Course: This course focus on all Verilog language constructs from practical usage perspective. Training involves 25+ design coding examples focused in fresher interviews.
System Verilog Course : This course gives fresher with required exposure to advanced functional verification concepts. All language constructs are covered with detailed coding examples involving more than 200 examples. Course also offers exposure to standard on-chip communication protocols and verification IP development for AXI. UVM essentials course will emphasis on UVM language constructs and UVC development for AHB Protocol.
RTL Debug Course: Will focus on training student with important debug concepts including schematic tracing, RTL tracing, RTL & TB coding issues, etc.
Linux OS Course: This course will ensures that student gets accustomed to industry work environment. Training also includes exposure to Makefile, revision management and all essential UNIX concepts.
Scripting Course: This will focus PERL, Python and TCL essential concepts for the IC Design flow. It will help student gain exposure to file management, regular expressions, Object oriented PERL, PERL modules and PERL usage including Python and TCL skills for the industry. Soft skill training will prepare student on how to face interviews effectively, right body language, etc.
Flexible and Affordable Course Payments
- Pay through Debit/Credit Cards or Net Banking or through UPI payments.
- Avail No-cost EMI option with zero processing fee from our financial partners.
- You can choose 3 to 12 months of flexible EMI terms without paying any interest on your
- loan during your courses. Start making the payments once the placement is done.
- Group (3 or more enrollment together) and deep discounts for Engineering colleges
100% Placement Assistance
Our placements consultants works closely with the leading VLSI companies to meet their entry and mid-level skilled engineer hiring needs and arranges interview opportunities for our trained engineers. The hiring companies are from India, USA and worldwide.
We provide placement support as complementary service until the trained engineers gets job. For more information, please speak to our placement counsellors
Curriculum
- 23 Sections
- 40 Lessons
- 1 Week
- Module 1 - Introduction to LinuxLessons, Quizzes, Exams and Practical's/Lab using computer/machines and EDA tools in a Module10
- 1.0Lesson 1 – Components of the UNIX/Linux System30 Minutes
- 1.1Lesson 2 – Directory & File Structure30 Hours
- 1.2Lesson 3 – Utilities and Commands1 Hour
- 1.3Lesson 4 – VI and VIM Editors1 Hour
- 1.4Lesson 5 – Basics of Shell Scripting2 Hours
- 1.5Quiz Set 110 Minutes3 Questions
- 1.6Quiz Set 210 Minutes1 Question
- 1.7Homework 1
- 1.8Homework 2
- 1.9Lab 1
- Module 2 - Digital Design15
- 2.0Lesson 1 – Introduction to Digital Design
- 2.1Lesson 2 – Number Systems
- 2.2Lesson 3 – Binary Codes
- 2.3Lesson 4 – Introduction to Boolean Algebra
- 2.4Lesson 5 – Gate level Optimization
- 2.5Lesson 6 – Combinational Circuits
- 2.6Lesson 7 – Sequential Circuits
- 2.7Lesson 8 – Memories
- 2.8Lesson 9 – Finite State Machine
- 2.9Lesson 10 – Data Converters
- 2.10Quiz Set 110 Minutes0 Questions
- 2.11Quiz Set 210 Minutes0 Questions
- 2.12Homework 1
- 2.13Homework 2
- 2.14Lab 1
- Module 3 - Introduction to VLSI11
- 3.0Lesson 1 – Introduction to VLSI
- 3.1Lesson 2 – VLSI Design Flow
- 3.2Lesson 3 – ASIC vs FPGA
- 3.3Lesson 4 – RTL Design Methodologies
- 3.4Lesson 5 – Introduction to ASIC Verification Methodologies
- 3.5Lesson 6 – VLSI Design Flow Steps – Demo
- 3.6Quiz Set 110 Minutes0 Questions
- 3.7Quiz Set 210 Minutes0 Questions
- 3.10Homework 1
- 3.11Homework 2
- 3.12Lab 1
- Module 4 - Verilog Language Introduction8
- Module 5 - Verilog Design and Verification Projects0
- Module 6 - System Verilog (SV) Language Introduction0
- Module 7 - Introduction to UVM0
- Module 8 - AXI Protocol & AXI VIP & TB Development0
- Module 9 - ASIC Verification Concepts0
- Mid Term Exam0
- Module 10 - Ethernet, MAC Core Functional Verification using SV & UVM0
- Module 11 - RTL Debug Concepts0
- Module 12 - SoC Verification Concepts0
- Module 13 - ASIC Flow0
- Module 14 - Perl, Python & TCL Scripting Introduction0
- Module 15 - Job Assistance and Soft Skill Training0
- Module 16 - Course Assignments0
- Final Practice and HomeworkCollection of practice questions including homework1
- Final EDA LabsCollection of Practical and EDA Lab1
- Final Exam0
- Final Project Work SubmissionCollection of Project Works1
- Final Project Work Presentation0
- Demo VideoCollection of Demo Videos and Tutorials1
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