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- VLSI Design and Verification
Curriculum
- 23 Sections
- 40 Lessons
- 1 Week
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- Module 1 - Introduction to LinuxLessons, Quizzes, Exams and Practical's/Lab using computer/machines and EDA tools in a Module10
- 1.0Lesson 1 – Components of the UNIX/Linux System30 Minutes
- 1.1Lesson 2 – Directory & File Structure30 Hours
- 1.2Lesson 3 – Utilities and Commands1 Hour
- 1.3Lesson 4 – VI and VIM Editors1 Hour
- 1.4Lesson 5 – Basics of Shell Scripting2 Hours
- 1.5Quiz Set 110 Minutes3 Questions
- 1.6Quiz Set 210 Minutes1 Question
- 1.7Homework 1
- 1.8Homework 2
- 1.9Lab 1
- Module 2 - Digital Design15
- 2.0Lesson 1 – Introduction to Digital Design
- 2.1Lesson 2 – Number Systems
- 2.2Lesson 3 – Binary Codes
- 2.3Lesson 4 – Introduction to Boolean Algebra
- 2.4Lesson 5 – Gate level Optimization
- 2.5Lesson 6 – Combinational Circuits
- 2.6Lesson 7 – Sequential Circuits
- 2.7Lesson 8 – Memories
- 2.8Lesson 9 – Finite State Machine
- 2.9Lesson 10 – Data Converters
- 2.10Quiz Set 110 Minutes0 Questions
- 2.11Quiz Set 210 Minutes0 Questions
- 2.12Homework 1
- 2.13Homework 2
- 2.14Lab 1
- Module 3 - Introduction to VLSI11
- 3.0Lesson 1 – Introduction to VLSI
- 3.1Lesson 2 – VLSI Design Flow
- 3.2Lesson 3 – ASIC vs FPGA
- 3.3Lesson 4 – RTL Design Methodologies
- 3.4Lesson 5 – Introduction to ASIC Verification Methodologies
- 3.5Lesson 6 – VLSI Design Flow Steps – Demo
- 3.6Quiz Set 110 Minutes0 Questions
- 3.7Quiz Set 210 Minutes0 Questions
- 3.10Homework 1
- 3.11Homework 2
- 3.12Lab 1
- Module 4 - Verilog Language Introduction8
- Module 5 - Verilog Design and Verification Projects0
- Module 6 - System Verilog (SV) Language Introduction0
- Module 7 - Introduction to UVM0
- Module 8 - AXI Protocol & AXI VIP & TB Development0
- Module 9 - ASIC Verification Concepts0
- Mid Term Exam0
- Module 10 - Ethernet, MAC Core Functional Verification using SV & UVM0
- Module 11 - RTL Debug Concepts0
- Module 12 - SoC Verification Concepts0
- Module 13 - ASIC Flow0
- Module 14 - Perl, Python & TCL Scripting Introduction0
- Module 15 - Job Assistance and Soft Skill Training0
- Module 16 - Course Assignments0
- Final Practice and HomeworkCollection of practice questions including homework1
- Final EDA LabsCollection of Practical and EDA Lab1
- Final Exam0
- Final Project Work SubmissionCollection of Project Works1
- Final Project Work Presentation0
- Demo VideoCollection of Demo Videos and Tutorials1
Lesson 1 – Verilog Language Basics
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