Development of Testbench using System Verilog
1. What is ‘logic’ type ? Discuss the advantages of ‘logic’ type in systemverilog ? What is the limitation of ‘logic’ type ?
Logic type is a new type in system verilog – it is a4-statetype like reg and wire.
It can be used in continuous assignment as well as in always block. Limitation is that it cannot be driven by multiple assignment statements, because there is no resolution as inwire, wand and wor type.
2. What is 4-state logic ? What is the advantage of 4-state over 2-state logic ? What is the advantage of 2-state over 4-state. Give example of 4-state type ? Give example of 3 2-state types in SystemVerilog.
4-state logic has 4 states – 0,1,x,z. X for unknown and z for high impedance. Advantages of 4-state over 2-state are –it can detect unintentional shorts, unreachable logicthroug h the’x’ state, also ‘z’ can model high impedance. ‘logic’ type is 4-state. 2-state logic simulates much faster than 4-state and uses
less memory. Example of 2-state types in systemverilog – bit, byte, int, shortint
3. What is always_comb ? Give 3 advantages of always_comb over always block.
always_comb can be used in place of alwaysblock when only combinational logic is intended.
always_comb –no needto specify thesensitivitylist, iflatchis detectedthen compiler will give an error, designer intent is clear – also it is simulated once at time 0.
4. Write SystemVerilog model of a 20-bit program counter with asynchronous reset using logic type, clock signal is clk.
logic [19:0] pc;
logic clk, reset;
always_ff (posedge clk, negedge reset)
if (!reset) pc = ‘0;
else pc = pc + 1;
5. What is enumerated type ? Define enumerated type for the following set of opcodes –
ADD=2, SUB=3,
JE=10, JNE-11, LD=12, ST=13 with type logic and size 4 bits.
Enumerated type is a set of symbols or labels or names – each name can be assigned a value.
The base type is int, the first symbol has value 0.
enum logic[3:0] {ADD=4’b0010, SUB, JE=4’b1010, JNE, LD, ST}} opcode;